// 三合1

module TOP (clk,
            rst_n,
            V);
    
    input   clk,rst_n;
    output V;

    wire clk_2p048;
    wire random;

    div50to2p048 U1 (
        .clk_50(clk),
        .clk_2p048(clk_2p048),
        .rst_n(rst_n)
    );

    random U2(
        .clk(clk_2p048),
        .rst_n(rst_n),
        .out(random)
    );

    sequential_detector U3(
        .clk(clk_2p048),
        .rst_n(rst_n),
        .in(random),
        .out(V)
    );
    
    
endmodule //TOP
